Data processing apparatus

ABSTRACT

A data processing apparatus has a first processing unit for processing an input data, a second processing unit responsive to the data processed by the first processing unit for executing a processing dependent on the data and producing a display data, and a display unit having a display drive unit and a display device for displaying the display data. The second processing unit is selectively inactivated and activated under control of the first processing unit to reduce power consumption in the second processing unit. The display drive unit is also selectively inactivated and activated under control of the first processing unit to reduce power consumption in the display unit. The display device has a memory function that maintains its display image even when supply of a display drive signal from the display drive unit is stopped, so that a latest image before inactivation of the second processing unit and/or the display drive unit for power consumption reduction is visible by an operator during the inactivated and low power consumption state of the apparatus.

This is a Rule 53b Divisional application of Ser. No. 10/772,364 filedFeb. 6, 2004, which is a Rule 53b Divisional application of Ser. No.10/194, 687 filed Jul. 24, 2002 which is a Rule 53b Divisionalapplication of Ser. No. 09/583,168 filed May 30, 2000 (issued on Mar.18, 2003, U.S. Pat. No. 6,535,985), which is a Rule 53b Continuationapplication of Ser. No. 08/283,165 filed Aug. 3, 1994 which isabandoned, which is a Rule 62 Continuation application of Ser. No.07/671,929 filed Mar. 20, 1991 which is abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data processing apparatus providedwith a display device.

2. Description of the Prior Art

Among compact and lightweight microcomputers, portable type computerspowered by batteries are now used extensively. Particularly, one of themknown as a note-size computer is lighter in weight and smaller in size,yet provides equal capabilities to those of a desktop or laptopcomputer. The note-size computer powered by batteries is handy for usein a place where a power supply facility is rarely available, e.g. ameeting room or a lecture hall.

However, the disadvantage of such handy use is that the life ofbatteries is short and limited. When used to record a business meetingor a college lecture, the service duration of such a note-size computerwith fully charged batteries is preferably 10 hours nonstop; morepreferably, 20 to 30 hours. If possible, more than 100 hours-a standardof hand calculators-is most desired.

So far, the service operation of a commercially available note-sizecomputer lasts 2 to 3 hours at best. This results in battery runout inthe middle of a meeting or college lecture causing an interruptionduring input work. As a result, troublesome replacement of batterieswith new ones will be needed at considerable frequency.

Such a drawback of the note-size computer tends to offset theportability in spite of its light weight and compactness.

It is understood that known pocket-type portable data processingapparatuses including hand calculators and electronic notebooks are muchslower in processing speeds than common microcomputers and thus, exhibitless power requirements. They are capable of servicing for years withthe use of a common primary cell(s) of which life will thus be no matterof concern. The note-size computer, however, has a processing speed ashigh as that of a desktop computer and consumes a considerable amount ofelectric energy-namely, 10 to 1000 times the power consumption of anypocket-type portable data processing apparatus. Even with theapplication of up-to-date high quality rechargeable batteries, theserving period will be 2 to 3 hours at maximum. This is far from adesired duration demanded by the users. For the purpose of compensatingthe short life of batteries, a number of techniques for energy savinghave been developed and some are now in practical use.

The most well known technique will now be explained.

A “resume” function is widely used in a common note-size computer. Itworks in a manner that when no input action continues for, a givenperiod of time, the data needed for restarting the computer withcorresponding information is saved in a nonvolatile IC memory and then,a CPU and a display are systematically turned off. For restart, a powerswitch is closed and the data stored in the IC memory is instantlyretrieved for display of the preceding data provided beforedisconnection of the power supply. This technique is effective forextension of the battery servicing time and suitable in practical use.

However, a specified duration, e.g. 5 minutes, of no key entry resultsin de-energization of the entire system of the computer and thus,disappearance of display data. Accordingly, the operator losesinformation and his input action is interrupted. For reviewing thedisplay data or continuing the input action, the power switch has to beturned on each time. This procedure is a nuisance for the operator. Theresume technique is advantageous in saving energy of battery power butvery disadvantageous in operability of the note-size computer.

More specifically, the foregoing technique incorporates as a means forenergy saving a system which de-energizes all the components including aprocessing circuit and a display circuit. The operator is thus requestedto turn on the power switch of the computer at considerable frequenciesduring intermittent data input action because each no data entryduration of a given length triggers automatic disconnection of theswitch. In particular, the data input operation with a note-sizecomputer is commonly intermittent and thus, the foregoing disadvantagewill be much emphasized.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improved dataprocessing apparatus capable of substantially reducing power consumptionwhile performing required data processing operations.

A data processing apparatus according to the present inventioncomprises: a data input unit for input of external data; a firstprocessing unit for processing the data inputted through the data inputunit; a second processing unit for processing the data inputted throughthe data input unit and/or an output data of the first processing unit;and a display unit for displaying an output data of the first and/orsecond processing units, wherein the display unit has a memory functionfor maintaining a display state without being energized, and the firstprocessing unit has a means for actuating the second processing unitaccording to a timing or a kind of the input data.

For example, when no data entry continues, the second processing unit orthe display unit is inactivated or decreased in clock rate thusdiminishing power consumption. Also, the present invention allows thedisplay of data to remain intact. Upon occurrence an input data, thefirst processing unit activates the second processing unit to processthe data. Thus, the operator can prosecute his job without knowledge ofan interrupted de-energization. As a result, an appreciable degree ofenergy saving is guaranteed without affecting the operability and thus,the service life of batteries will largely be increased.

In another aspect, the first processing unit may activate the secondprocessing unit according to the kind of the input data. When the inputdata is such a data that requires a processing in the second processingunit, the first processing unit activates the second processing unit.The second processing unit, after completing a required operation orprocessing, may enter an inactive state by itself or may be forced intothe inactive state by the first processing unit. Thus, the powerconsumption will be reduced to a considerable rate without affecting theoperability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a data processing apparatus showing a firstembodiment of the present invention;

FIG. 2 is a timing chart;

FIG. 3 is a view showing the arrangement of a display unit;

FIG. 4 is a cross sectional view explaining the operating principle ofthe display unit;

FIGS. 5(a) and 5(b) are views showing displayed images on the displayunit;

FIG. 6 is a flow chart;

FIG. 7-a is a block diagram showing an arrangement of components;

FIG. 7-b is a block diagram showing another arrangement;

FIG. 7-c is a block diagram showing a further arrangement;

FIG. 7-d is a flow chart;

FIG. 8(a) through 8(f) illustrate the operating principle of areflective device with the use of different reflecting plates;

FIG. 9 is a block diagram showing a second embodiment of the presentinvention;

FIG. 10-a is a block diagram associated with a first processing unit;

FIG. 10-b is a block diagram associated with a second processing unit;

FIGS. 11-a and 11-b are flow charts:

FIG. 12 is a timing chart;

FIG. 13 is a view explaining the representation of a cursor;

FIG. 14 is a view showing a sequence of translation procedures;

FIG. 15 is a view explaining data insertion;

FIG. 16 is a view explaining a copy mode;

FIG. 17 is a block diagram showing a modification of the secondembodiment;

FIG. 18 is a block diagram showing a third embodiment of the presentinvention;

FIG. 19 is a flow chart;

FIG. 20 is a block diagram showing a fourth embodiment of the presentinvention;

FIG. 21 is a timing chart of the fourth embodiment;

FIG. 22 is a block diagram showing a fifth embodiment of the presentinvention;

FIG. 23 is a timing chart of the fifth embodiment;

FIG. 24 is a block diagram showing a data input unit; and

FIG. 25 is a block diagram showing a combination of the first and secondprocessing units.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be describedreferring to the accompanying drawings.

Embodiment 1

FIG. 1 is a block diagram of a data processing apparatus showing a firstembodiment of the present invention.

The data processing apparatus comprises a data input unit 3, a firstprocessing block 1, a second processing block 98, and a display block99.

In operation, a data input which is fed to the data input unit 3 of thedata processing apparatus by means of key entry with a key-board orcommunications interface is transferred to the first processing block 1in which a first processor 4 examines which key in key entry is pressedor what sorts of data are input from the outside and determines thesubsequent procedure according to the information from a first memory 5.

If no input is supplied to the data input unit 3 throughout a givenperiod of time as shown in FIG. 2-a and also, the action of a secondprocessor 7 has been completed, the feeding of clock signals to thesecond processor 7 and a display circuit 8 is halted by an interruptioncontroller 6 and/or a process of energy saving is systematicallyexecuted.

The energy saving process will now be described referring to FIG. 2.

As shown in FIG. 2-a, a data input entered at t1 using an n-th key ofthe key-board is transferred from the data input unit 3 to the firstprocessor 4.

The first processor 4 when examining the data input and determining thatfurther processing at the second processor 7 is needed delivers a startinstruction via the interruption controller 6 and a start instructionline 80 to the second processor 7 which thus commences receiving thedata input from the first processor 4. The second processor 7 startsprocessing the data input when t=t3 as shown in FIG. 2-c and uponfinishing, sends an end signal to the first processor 4. In turn, eitherthe first processor 4 or the interruption controller 6 delivers a stopinstruction to the second processor 4 via the startup instruction line80. Accordingly, the second processor 4 transfers finally processed datafrom its RAM memory or register to the second memory for temporarystorage and then, stops processing action when t=t5 as shown in FIG. 2-cor enters into an energy saving mode where a consuming power is sharplyattenuated. After t5 where the actuation of the second processor 7 isceased, the data remains held in the second memory 9 due to itsnonvolatile properties or due to the action of a back-up battery. Ifdisplay change is needed, the second processor 4 sends a display changesignal to the first processor 4. The first processor 4 then delivers adisplay start instruction via a display start instruction line 81 to thedisplay circuit 8 for starting actuation. When t=t4 as shown in FIG.2-d, the command signal is transmitted to the display circuit 8 which inturn retrieves the data of a previous display text from a video memory82 or the second memory 9 and displays a new image corresponding to thedisplay change signal and data from the second processor 7. When t=t6,the display circuit 8 sends its own instruction or an end signal via theinterruption controller 6 to the first processor 4 and upon receiving aninstruction from the first processor 4, stops or diminishes clockgeneration to enter a display energy saving mode. Thereafter, the powerconsumption of the display circuit 8 will largely be declined asillustrated after t6 in FIG. 2-d.

After t6, the display circuit 8 stays fully or nearly inactivated but adisplay 2 which is substantially consisted of memory retainable devices,e.g. ferroelectric liquid crystal devices, continues to hold the displayimage. The arrangement of the display 2 will now be described. Thedisplay 2, e.g. a simple matrix type liquid crystal display, contains amatrix of electrodes in which horizontal drive lines 13 and verticaldrive lines 14 coupled to a horizontal driver 11 and a vertical driver12 respectively intersect each other, as best shown in FIG. 3. FIG. 4illustrates a pixel of the display 2 in action with a voltage beingapplied.

In each pixel, a ferroelectric liquid crystal 17 is energized by thetwo, horizontal and vertical lines 13, 14 which serve as electrodes andare provided on glass plates 15 and 16 respectively.

More particularly, FIG. 4-a shows a state where light is transmittedthrough. When a signal is given, the ferroelectric liquid crystal 17changes its crystalline orientation and acts as a polarizer in which anangle of polarization is altered, thus allowing the light to passthrough.

When a voltage is applied in the reverse direction, the ferroelectricliquid crystal 17 causes the angle of polarization to turn 90 degreesand inhibits the passage of light with polarization effects, as shown inFIG. 4-b. The ferroelectric liquid crystal 17 also has a memoryretainable effect as being capable of remaining unchanged in thecrystalline orientation after the supply of voltage is stopped, as shownin FIG. 4-c. Accordingly, throughout a duration from t=t6 to t=t14,explained later, the display remains intact without any operation of thedisplay circuit 8. While the energy saving mode is involved after t6,both the data input unit 3 and the first processor 4 are only in action.

The first processor 4 performs only conversion of key entry to lettercode or the like. In general, the key entry is conducted by a humanoperator and executed some tens times in a second at best. The speed ofdata entry by a human operator is 100 times or more slower than theprocessing speed of any microcomputer. Hence, the processing speed ofthe first processor 4 may be as low as that of a known hand calculatorand the power consumption will be decreased to hundredths or thousandthsof one watt as compared with that of a main CPU in a desktop computer.As shown in FIG. 2-b, the first processor 4 continues operating while apower switch 20 of the data processing unit 1 is closed. However, itconsumes a lesser amount of energy and thus, the power consumption ofthe apparatus will be low.

When n+1-th key entry is made at t11, the first processor 4 examines thedata of the entry at t12 and if necessary, delivers a start instructionvia the interruption controller 6 or directly to the second processor 7for actuation. Upon receiving the start instruction, the secondprocessor 7 starts processing again with the use of clock signals sothat the data stored in the second memory 9, i.e. data at a previousstop when t=t5, such as memory data, register information, or displaydata, is read out and the CPU environment when t=t5 can fully berestored. When t=t 13, the data in the first processor 4 is transferredto the second processor 7 for reprocessing. The second processor 7 isarranged to operate at high speeds and its power consumption is as highas that of a desk-top computer. If the second processor 7 iscontinuously activated, the life of batteries will be shortened as wellas in a known note computer. The present invention however provides aseries of energy saving mode actions during the operation, whereby theenergy consumption will be minimized.

The energy saving mode is advantageous. For example, the durationrequired for processing the data of a word processing software iscommonly less than 1 ms while the key entry by a human operator takesseveral tens of milliseconds at maximum. Hence, although the peak ofenergy consumption during a period from t 13 to t 15 is fairly high inthe second processor 7 as shown in FIG. 2-c, the average is not morethan a tenth or a hundredth of the peak value. It is now understood thatthe energy saving mode allows lower power consumption.

When t=t14, the second processor 7 sends a desired portion of thedisplay data to the display 2. Before t14, the display 2 continues todisplay the text altered at t6 due to the memory effects of theferroelectric liquid crystal 17 while the display circuit 8 remainsinactivated. The desired data given through the key entry at t11 iswritten at t14 for regional replacement. The replacement of one toseveral lines of display text is executed by means of voltageapplication to corresponding numbers of the horizontal and verticaldrive lines 13 and 14. This procedure requires a shorter period ofprocessing time and thus, consumes a lesser amount of energy as comparedwith replacement of the entire display text.

The second processor 7 then stops operation when t=t15 and enters intothe energy saving mode again as shown in FIG. 2-c.

At the moment when the operation of the second processor 7 has beenfinished before t15 or when a stop instruction from the first processor4 is received, the second processor 7 saves the latest data in thesecond memory 9.

When t=t14, the second processor 7 stops operation or diminishes anoperating speed and enters into the energy saving mode.

When the input data is fed at short intervals, e.g. at t21, t31, t41,and t51, through a series of key entry actions or from a communicationsport, the second processor 7 shifts to the energy saving mode at t23,t33, and t43 as shown in FIG. 2-c. If the first processor 4 detects thatthe interval between data inputs is shorter than a predetermined time,it delivers an energy saving mode stop instruction to the secondprocessor 7 which thus remains activated without forced de-energizationand no longer enters into the energy saving mode. The energy saving modeis called back only when the interval between two data inputs becomessufficiently long.

Also, when the first processor 4 detects that the key entry is absentduring a given length of time, it actuates to disconnect the powersupply to primary components including the first processor 4 for shiftto a power supply stop mode. The memory data is being saved by theback-up battery while the power supply is fully disconnected.

Before disconnection of the power supply, the first processor 4 howeversends a power supply stop display instruction directly or via the secondprocessor 7 to the display circuit 8 for display of an “OFF” sign 21shown in FIG. 5-b and then, enters into the power supply stop mode. TheOFF sign 21 remains displayed due to the memory effects of the display 2after the power supply is disconnected, thus allowing the operator todistinguish the power supply stop mode from the energy saving mode.

In the energy saving mode, the operation can be started again by keyentry action and thus, the operator will perceive no interruption in theprocessing action.

In the power supply stop mode, the OFF sign 21 is displayed and theoperator can restart the operation in succession with the previous dataretrieved from the second memory 9 by the second processor 9 when thepower switch 20 is turned on. This procedure is similar to that in theconventional “resume” mode.

The foregoing operation will now be described in more detail referringto a flow chart of FIG. 6. When the power switch 20 is turned on at Step101, the first processor 4 starts activating at Step 102. The input datagiven by key entry is transferred from the data input unit 3 to thefirst processor 4 at Step 103. At Step 104, it is examined whether theduration of no-data entry lasts for a predetermined time or not. If theno-data entry duration t is greater than the predetermined time, theprocedure moves to Step 105 where the actuation of the second processor7 is examined. If the second processor 7 is in action, the proceduremoves back to Step 103. If not, the entire apparatus is de-energized, atStep 106, and stops actuating at Step 107 before restarting with Step101 where the power supply switch 20 is closed.

If the no-data entry duration t is greater than the predetermined time,but is as short as a few minutes, the procedure is shifted from Step 104to Step 108. When the processing frequency in the first and secondprocessors 4 and 7 is low, the procedure moves from Step 108 to Step 109where a back light is turned off for energy saving.

If the no-data entry duration t is not greater than the predeterminedtime, the operation in the first processor 4 is prosecuted at Step 110.Also, it is examined at Step 110 a whether the data of text is keptdisplayed throughout a considerable length of time or not. If too long,refreshing action of the data display is executed at Step 110 b forprevention of an image burn on the screen. At Step 110 c, the processingfrequency in the second processor 7 is examined and if it is high, thesecond processor 7 is kept in action at Step 11 d. If the processingfrequency is low, the procedure moves to Step 111. When it is determinedat Step 111 that no further processing in the second processor 7 isneeded, the procedure returns to Step 103.

When further processing in the second processor 7 is required, theprocedure moves from Step 111 to Step 112 a where the actuation of thesecond processor 7 is examined. If the second processor 7 is not inaction, a start instruction is fed at Step 112 b to the second processor7 which is in turn activated at Step 113 by the first processor 4 andthe interruption controller 6. The second processor 7 then startsprocessing action at Step 114. If it is determined at Step 115 that achange in the text of display is needed, the procedure moves to Step 116a where a display change instruction is supplied to both theinterruption controller 6 and the first processor 4. Then, theinterruption controller 6 delivers a display energizing instruction tothe display block 99 at Step 116 b. The display circuit 8 is activatedat Step 116 c and the display change on the display 2 including thereplacement of a regional data with a desired data is carried out atStep 117. After the display change is checked at Step 118, a displaychange completion signal is sent to the first processor 4 at Step 117 a.When the display change completion signal is accepted at Step 117 b, thedisplay 2 is turned off at Step 119.

If no change in the display text is needed, the procedure moves fromStep 115 to Step 120 where the completion of the processing in thesecond processor 7 is examined. If yes, a processing completion signalis released at Step 120 a. As a result, the second processor 7 stopsoperation at Step 121 upon receiving a stop signal produced at Step 120b and the procedure returns back to Step 103.

FIGS. 7-a and 7-b are block diagrams of a note-size computer accordingto the first embodiment of the present invention.

As shown in FIG. 7-a, a data input block 97 comprises a keyboard 201, acommunication port 51 with RS232C, and a floppy disk controller 202.Also, a hard disk unit 203 is provided separately. A first processingblock 1 is mainly consisted of a first processor 4. A second processingblock 98 contains a second processor 7 which is a CPU arranged for shiftto and back from the energy saving mode upon stopping and feeding of aclock signal respectively and is coupled to a bus line 210. Also, a ROM204 for start action, a second memory 9 of DRAM, and a backup RAM 205which is an SRAM for storage of individual data of returning from theresume mode are coupled to the bus line 210. Both ends of the bus line210 are connected to the first processor 4 and a display block 99respectively. The display block 99 has a graphic controller 206 and aliquid crystal controller driver 207 arranged in a display circuit.There are also provided a video RAM 209 and a liquid crystal display208. For energy saving operation, corresponding components only in thearrangement are activated while the remaining components arede-energized. This energy saving technique is illustrated in more detailin Table 1. In general, input operation for e.g. word processinginvolves an intermittent action of keyboard entry. Hence, the powersupply is connected to every component except the communications I/Ounit. While a clock signal is fed to the first processing block 1, noclock signals are supplied to the second processing block 98 and thedisplay block 99. Power is thus consumed only in the first processingblock 1. If necessary, the second block 98 and/or the display block 99are activated within a short period of time. If more frequent operationsare needed, the second processing block 98 is kept activated foracceleration of processing speeds.

Then the key entry is absent for a given time, the second processingblock 98 is disconnected and simultaneously, its processing data isstored in a backup memory for retrieval in response to the next keyentry.

FIG. 7-b is similar to FIG. 7-a, except that the first processor 4having a lower clock frequency is used as a “monitor” for the totalsystem and the processing will be executed by the second processor 7having a higher clock frequency. The first processor 4 is adapted foroperating an event processing method by which the second processor 7 isactivated for processing action corresponding to data of the keyboardentry. The second processor 7 stops operation for the purpose of energysaving when the processing action is finished and remains inactivateduntil another key entry commences. The display block 99 starts operatingin response to a display signal from the second processor 7 and stopsautomatically after completion of display. This procedure can beexecuted with a common operating system similar to any known operatingsystem, thus ensuring high software compatibility. For example, MS-DOSis designed to run with the use of one complete CPU. Hence, the energysaving effect will hardly be expected during operation with conventionalapplication software programs. It is then a good idea that a specificoperating system and a corresponding word processing software which areinstalled in two CPUs are provided in addition to the conventionaloperating system. Accordingly, a word processing job can be performedusing the specific software with the operating system of the presentinvention and thus, the power consumption will be reduced to less than atenth or hundredth. Also, general purpose software programs can workwith the conventional operating system-although the energy saving effectwill be diminished. It would be understood that about 80% of the job ona note-size computer is word processing and the foregoing arrangementcan contribute to the energy saving.

FIG. 7-c is a block diagram of another example according to the firstembodiment and FIG. 7-d is a flow chart showing a procedure with the useof a conventional operating system such as MS-DOS. The second processor7 is a CPU capable of holding data from its register and internal RAMduring actuation of no clock or de-energization. When key entry is madeat Step 251, a keyboard code signal from the keyboard 201 is transferredby the first processor 4 to a start device 221 which remains activated,at Step 252. At Step 253, the start device 221 delivers a clock signalto a main processor 222 which is de-energized. Both of the register 223and the internal RAM 224 are coupled to a backup source and thus, startoperating upon receipt of the clock signal. At Step 254, the mainprocessor 222 starts the program which has been on stand-by for keyentry. The program is then processed for e.g. word processing accordingto data of the key entry, at Step 255. At Step 257, a displayinstruction is released for replacement of display text if required atStep 256. At Step 258, the graphic controller 206 is activated. The datain the video RAM 209 is thus rewritten at Step 259. After the liquidcrystal controller driver 207 is activated at Step 261, a desired changein the display text is made on the liquid crystal display 208 formed offerroelectric liquid crystal. Then, the video RAM 209 is backupenergized at Step 262 and the display block 99 is de-energized, at Step263, thus entering into the energy saving mode. When the processing inthe second processor 7 is completed at Step 270, the program stops andmoves into a “keyboard entry stand-by” stage at Step 271. At Step 272,the data required for re-actuation of the register 223 and the internalRAM 234 is saved and the second memory 9 is backup energized before aclock in the CPU is stopped. Then, the second processor 7 stopsoperation, at Step 273, thus entering into the energy saving mode. Asthe start device 221 remains activated, the second processor 7 stays onstand-by for input through keyboard entry at Step 251 or from thecommunications port 5. As understood, the start device 221 only is keptactivated in the second processing block 98. The CPU shown in FIG. 7-cprovides backup of registers with its clock unactuated and ensuresinstant return to operation upon actuation of the clock. As a singleunit of the CPU is commonly activated, a conventional operating systemcan be used with equal success. Also, existing software programsincluding word processing programs can be processed with less assignmentand thus, private data stock will be permitted for optimum use.Consequently, it would be apparent that this method is eligible. Inaddition, the consumption of electric energy will be much decreasedusing a technique of direct control of the first processor 1 on displaytext change which will be described later with a second embodiment ofthe present invention. As understood, the resume mode allows mostcomponents to remain de-energized when no keyboard entry lasts for along time.

As a ferroelectric liquid crystal material has a memory effect,permanent memory results known as protracted metastable phenomenon willappear when the same text is displayed for a longer time. For preventionof such phenomenon, a display change instruction is given to the firstprocessor 4 and the power switch 20 upon detection with the timer 22that the display duration exceeds a predetermined time in the energysaving mode or power supply stop mode. Accordingly, the display circuit8 actuates the display 2 to change the whole or a part of the displaytext, whereby permanent memory drawbacks will be eliminated.

If it is happened that the persistence of such permanent memory effectsallows no change in the display text on the display 2, the crystallineorientation of liquid crystal is realigned by heating up the display 2with a heater 24 triggered by a display reset switch 23. Then, arbitrarychange in the display text on the display 2 will be possible.

Energy saving can be promoted by stopping the clock in the secondprocessor 7 during the energy saving mode. When more or full energysaving is wanted, the power supply to the second processor 7 or thedisplay circuit 8 is disconnected by the interruption controller 6.

As understood, the power supply stop mode requires a minimum of powerconsumption for backup of the second memory 9.

As shown in FIG. 1, the back light 25 is turned off when the powersource is a battery and a reflective device 27 is activated by areflection circuit 26 for display with a reflection mode.

The reflective device 27 is composed of a film of ferroelectric liquidcrystal which provides a transparent mode for transmission of light, asshown in FIG. 8-a, and an opaque mode for reflection as shown in FIG.8-b, for alternative action. Incoming light 32 is reflected on thereflective device 27 and runs back as reflected light 33. At this time,polarization is also effected by the polarizers in the display 2 and thereflective device 27, whereby the number of components will be reduced.Also, a film-form electrochromic display device may be used forproviding a transmission mode and a white diffusion screen mode in whichit appears like a sheet of white paper.

The reflective device 27 may be of fixed type, as shown in FIGS. 8-c and8-d, comprising a light transmitting layercomposed of low refractiontransmitting regions 28 and high refraction transmitting regions 29 anda reflecting layer 31 having apertures 30 therein.

As shown in FIG. 8-c, light emitted from the back light 25 enters thehigh refraction transmitting regions 29 where it is fully reflected onthe interface between the high and low refraction transmitting regions29, 28 and passes across the apertures 31 to a polarizer plate 35. Thepolarized light is then transmitted to a liquid crystal layer 17 forproducing optical display with outwardly emitted light.

During the reflection mode in battery operation, outside light 32 passesthe liquid crystal layer 17 and is reflected by the reflecting layer 31formed by vapor deposition of aluminum and reflected light 33 runsacross the liquid crystal layer 17 again for providing optical display.

The reflective device 27 requires no external drive circuit, thuscontributing to the simple arrangement of a total system. It is knownthat such a combination of high and low refraction transmitting regionsis easily fabricated by a fused salt immersion method which is commonlyused for making refraction distributed lenses.

Although such a transmission/reflection combination type liquid crystaldisplay is disadvantageous in the quality of a display image as comparedwith a transmission or reflection speciality type liquid crystaldisplay, the foregoing switching between transmission and reflectionallows display of as good an image as of the speciality type display inboth the transmission and reflection modes. This technique is thussuited to two-source, battery and AC application.

When the external power source is connected, the back light 25 is litupon receiving an instruction from the first processor 4 which alsodelivers a transmission instruction to the reflection circuit 26 andthus, the reflective device 27 becomes transparent simultaneously.Accordingly, transmitting light can illuminate the display as shown inFIG. 8-a.

When the battery is connected, the first processor 4 delivers areflection signal to the reflection circuit 26 and the reflective device27 becomes opaque to cause reflection and diffusion. As a result, thedisplay is made by reflected outside light as shown in FIG. 8-b while anamount of electric energy required for actuation of the back light 25 issaved.

Also, the same result as shown in FIGS. 8-c and 8-d may be provided withthe use of a transmitting reflective plate 34 which is formed of a metalplate, e.g. of aluminum, having a multiplicity of tapered roundapertures therein, as illustrated in FIGS. 8-e and 8-f.

As set forth above, the CPU in this arrangement provides intermittentactuation in response to the intermittent key entry and the averagepower consumption of the apparatus will be declined to an appreciablerate.

Also, the text remains on display during the operation and thus, theoperator can perceive no sign of abnormality when the processing unit isinactivated. More particularly, a great degree of energy saving will beensured without affecting the operability.

More particularly, each key entry action takes several tens ofmilliseconds while the average of CPU processing durations in wordprocessing is about tens to hundreds of microseconds. Hence, the CPU isactivated {fraction (1/100)} to {fraction (1/1000)} of the key entryaction time for accomplishing the task and its energy consumption willthus be reduced in proportion. However, while the energy consumption ofthe CPU is reduced to {fraction (1/1000)}, {fraction (1/10)} to{fraction (1/120)} of the overall consumption remains intact because thedisplay unit consumes about 10 to 20%, namely 0.5 to 1 W, of the entirepower requirement. According to the present invention, the display unitemploys a memory effect display device provided with e.g. ferroelectricliquid crystal and thus, its power consumption will be minimized throughintermittent activation as well as the CPU.

As the result, the overall power consumption during mainly key entryoperation for e.g. word processing will be reduced to {fraction (1/100)}to {fraction (1/1000)}.

Embodiment 2

FIG. 9 is a block diagram showing a second embodiment of the presentinvention.

In the second embodiment, the first processor 4 is improved in theoperational capability and the second processor 7 of which energyrequirement is relatively great is reduced in the frequency of actuationso that energy saving can be encouraged.

As shown in FIG. 9, the arrangement of the second embodiment isdistinguished from that of the first embodiment by having a signal line97 for transmission of a display instruction signal from the firstprocessing block 1 to the display block 99. In operation, the firstprocessor 4 of the first processing block 1 delivers a display changesignal to the display circuit 8 of the display block 99 for change ofthe display text on the display 2. As understood, the second processor 7delivers such a display change signal to the display circuit 8 accordingto the first embodiment.

FIG. 10-a is a block diagram showing in more detail the connection ofthe first processor 4, in which the first memory 5 comprises a firstfont ROM 40 for storage of dot patterns of alphabet and Japanesecharacter fonts or the like in a ROM, an image memory 41, and a generalmemory 42.

As shown in FIG. 10 b, the second memory 9 may contain a second font ROM43 which serves as a font memory.

In operation, a series of simple actions for display text change can beexecuted using the first processor 4. Character codes are produced inresponse to the key entry and font patterns corresponding to thecharacter codes are read from the first 40 or second font memory 43 fordisplay on the display 2 after passing the display circuit 8. The secondmemory 9 may also contain a second general memory 44.

During input of a series of data characters which requires no largescale of processing, the first processor 4 having less energyrequirement is actuated for operation of the display text change. Iflarge scale of processing is needed, the second processor 7 is thenutilized. Accordingly, the frequency of actuation of the secondprocessor 7 is minimized and energy saving will be guaranteed. Also, asshown in FIG. 11, the memory size of the first memory 5 can be decreasedbecause of retrieval of font patterns from the second font ROM 43 of thesecond memory 9.

The operation according to the second embodiment will now be describedin more detail referring to flow charts of FIGS. 11-a and 11-b. FIG.11-a is substantially similar to FIG. 6 which shows a flow chart in thefirst embodiment.

A difference is that as the first processor 4 directly actuates thedisplay circuit 8, a step 130 and a display flow chart 131 are added.When the first processor 4 judges that the display is to be changed inStep 130 and that a desired data for replacement in the display text issimple enough to be processed by the first processor 4 at Step 111, theprocedure moves to the display flow chart 131. The display flow chart131 will now be described briefly. It starts with Step 132 where thedisplay block 99 is activated. At Step 133, the display text is changedand the change is examined at Step 133. After the confirmation of thecompletion of the text change at Step 134, the display block 99 isde-energized at Step 135 and the procedure returns back to Step 103 forstand-by for succeeding data input. FIG. 11-b illustrates the step 133in more detail. After the display block 99 is activated, at Step 132, bya start instruction from the first processing block 1, the movement of acursor with no restriction is examined at Step 140. If yes, data inputthroughout the cursor movement is executed at Step 141. If not, it isthen examined whether the desired input area on the display 2 isoccupied by existing data or not at Step 142. This procedure can becarried out by reading the data in the image memory 41 with the firstprocessor 4. If no, partial text replacement with desired data isexecuted at Step 143. If yes, the procedure moves to Step 144 where theexisting data in the input area of the display block 99 is checked usingthe image memory 41 and examined whether it is necessarily associated ornot with the desired data to be input. If no, overwriting of the desireddata is executed at Step 143. If yes, the existing data is retrievedfrom the image memory 41 or read from the second font ROM 9 and coupledwith the desired data for composition, at Step 145. At Step 146, it isexamined whether a black/white inversion mode is involved or not. Ifyes, the data is displayed in reverse color at Step 147. If no, the textchange with the composite data is carried out at Step 148. Then, thecompletion of the text change is confirmed at Step 134 and the displayblock 99 is turned off at Step 99.

For a more particular explanation, the processing action ofcorresponding components when the key entry is made is illustrated inFIG. 12. When the key entry with “I” is conducted at t1 as shown in FIG.12-e, the first processor 4 shifts input data into a letter “I” code,reads a font pattern of the letter code from the first font ROM 40 shownin FIG. 10, and actuates the display circuit for display of the letter“I” on the display 2. With the memory effect display havingferroelectric crystal liquid, partial replacement in a character can bemade. The partial replacement is feasible in two different manners; onefor change dot by dot and the other for change of a vertical orhorizontal line of dots at once. The dot-by-dot change is executed withless energy requirement but at a higher voltage, thus resulting in highcost. The line change has to be done in the group of dots at once evenwhen one dot only is replaced but at relatively lower voltages. Bothmanners in this embodiment will now be explained.

When the horizontal and vertical drivers 11, 12 shown in FIG. 3 accepthigher voltages, it is possible to fill the dots forming the letter “I”one by one. Accordingly, the letter “I” can be displayed by having afont data of a corresponding character pattern supplied from the firstprocessor 4. However, ICs accepting such a high voltage are costly. Itis thus desired for cost saving that the operating voltage is low. It isnow understood that every data processing apparatus is preferablyarranged, in view of capability of up-to-date semiconductors, forproviding line-by-line text change operation.

It is also necessary that the first memory 5 of the first processor 4carries at least data of one text line.

For Japanese characters, the one text line data is equal to 640×24 dots.The writing of the letter “I” thus involves replacement of 24 of 640-ddot lines.

In operation, the previous data of a target line is retrieved from theimage memory 41 of the first memory 5 and also, the pattern data of theletter “I” is read from the first font ROM 40. Then, the two data arecombined together to a composite data which is then fed to the displaycircuit 8 for rewriting of one text line on the display 2.Simultaneously, the same data is stored into the image memory 41. Theinput of “I” is now completed.

None of the first font ROM 40 and the image memory 41 is needed when thesecond font ROM 43 is employed for the same operation, which is capableof processing coded data. In particular, the same text line can beexpressed with about 40 of 2-byte characters and thus, 40×2=80 bytes perline. Therefore, the first memory 5 may carry coded data of the entirescreen image.

During the processing of data input “I” in either of the two foregoingmanners, the second processor 7 provides no processing action as shownin FIG. 12-c.

Similarly, a series of key inputs are prosecuted by the first processor4, “space” at t2, “L” at t3, “i” at t4, “v” at t5, and “e” at t6.Although the first processor 4 is much slower in the processing speedthan the second processor 7, the replacement of one text line on displaycan be pursued at an acceptable speed with less energy consumption.

As shown in FIG. 12, t7 represents the key input of an instruction forprocessing a large amount of data, e.g. spelling check in wordprocessing, translation from Japanese to English, conversion of Japanesecharacters into Chinese characters, or calculation of chart data.

When the first processor 4 determines that the processing at the secondprocessor 7 is needed, the second processor 7 is turned on at t71. Thestart-up of the second processor 7 is the same as of Embodiment 1. Asshown in FIG. 12-c, the second processor 7 upon being activated at t71returns to the original state prior to interruption and startsprocessing the data of text lines fed from the first processor 4. As theprocessing is prosecuted, each character of changed text is displayed onthe display 2 through the display circuit 8 as shown at t72 in FIG.12-d.

This procedure will now be explained in the form of data entry fortranslation from Japanese to English. After the letter k is input at t1,as shown in FIG. 12-f, and displayed on the screen, as shown in FIG.12-h. Then, the letter a is input at t2 and the display reads “ka” asshown in FIG. 12-h.

By then, the second processor 7 remains inactivated as shown in FIG.12-c. When a key of translating conversion is pressed at t7, the secondprocessor 7 starts processing at t71. Accordingly, the Japaneseparagraph “kareha” is translated to “He is” in English. The resultantdata is sent to the display circuit 8 for dot-by-dot replacement fordisplay.

How, the display reads “He is” as shown in FIG. 12-h. The dot-by-dotcharacter replacement shown in FIG. 12-g requires less electric energythan the text line replacement shown in FIG. 12-d.

For the purpose of saving energy during the movement of the cursor, theblack/white inversion or negative mode is used as shown in FIGS. 13-aand 13-b. This however increases the power consumption in the linereplacement. When a bar between the lines is used for display of thecursor as shown in FIGS. 13-c and 13-d, the replacement of the full lineis not needed and thus, energy saving will be expected. Also, the speedof processing is increased and the response will speed up duringprocessing with the low speed first processor 4. This advantage isequally undertaken in the dot-by-dot replacement.

As shown in FIG. 14-a, the movement of the cursor is expressed by thebar. For ease of viewing, the bar may be lit at intervals by means ofcontrol with the first processor 4. When a key data input is given, acorresponding character is displayed in the reverse color as shown inFIG. 14-b. This technique will also reduce the energy consumption atleast during the cursor movement.

FIGS. 14-a to 14-g illustrate the steps of display corresponding to t1to t7. FIG. 14-h shows the conversion of the input text.

FIGS. 15-a to 15-f shows the insertion of a word during dot-by-dotreplacement. It is necessary with the use of the second font ROM 43 inthe arrangement shown in FIG. 10 that the data of one text line is savedin the image memory 41 because the first font ROM 40 does not carry allthe Chinese characters. When the cursor moves backward as shown in FIGS.15-c and 15-d, the letter n is called back from the image memory 41.Accordingly, the data prior to insertion can be restored without the useof the second processor 7 or the second front ROM 43 as shown in FIG.15-d.

FIGS. 16-a to 16-g show the copy of a sentence “He is a man”. Theprocedure from FIG. 16-a to FIG. 16-f can be carried out with the firstprocessor 4. The step of FIG. 16-g involves an insertion action which isexecuted by the second processor 7.

According to the second embodiment, most of the job which is processedby the second processor 7 in the first embodiment is executed by the lowpower consuming first processor 4. Thereby, the average energyconsumption will be much lower than that of the first embodiment.

The optimum of a job sharing ratio between the first and secondprocessors 4 and 7 may vary depending on particulars of a program fore.g. word processing or chart calculation. Hence, a share of the firstprocessor 4 in operation of a software program can be controlled byadjustment on the program so as to give an optimum balance between theenergy consumption and the processing speed. Also, a video memory 82 maybe provided in the display block 99 for connection via a connecting line96 with the first processor 4. This allows the data prior to replacementto be stored in the video memory 82 and thus, the image memory 41 shownin FIG. 10-a will be eliminated.

Embodiment 3

FIG. 18 is a block diagram showing a third embodiment of the presentinvention. The difference of the third embodiment from the first andsecond embodiments will now be described. As shown in FIG. 1, the firstembodiment has the display start instruction line 81 along which both astart instruction and a stop instruction are transferred from the firstprocessing block 1 to the display block 99 while equal instructions aretransferred by the start instruction line 80 from the same to the secondprocessing block 98.

The third embodiment contains no display start instruction line 81 tothe display block 99 as shown in FIG. 18. Also, the start instructionline 80 of the third embodiment allows only a start instruction but nota stop instruction to be transmitted from the first processing block 1to the second processing block 98.

The second processor 7 stops itself upon finishing the processing andenters into the energy saving mode. When the second processor 7determines that the display change is needed, it delivers a displaystart instruction via a data line 84 to the display block 99 which isthen activated. After the display change on the display 2 is completed,the display block 99 stops operation and enters into the display energysaving mode. This procedure will be explained in more detail using aflow chart of FIG. 19. The flow chart is composed of a first processingstep group 151, a second processing step group 152, and a thirdprocessing step group 153. At first, the difference of this flow chartwill be described in respect to the sequence from start to stop of thesecond processing block 98.

There is no control flow from the second processing step group 152 ofthe second processing block 98 to the first processing step group 151,unlike the flow chart of the first embodiment shown in FIG. 6. Morespecifically, the first processor 4 delivers, at Step 112, a startinstruction to the second processor 7 which is then activated. This stepis equal to that of the first embodiment. However, the second processor7 is automatically inactivated at Step 121, as compared withde-energization by an instruction from the first processor 4 in thefirst embodiment. At Step 103, the second processor 7 is turned to adata input stand-by state.

The difference will further be described in respect to the sequence fromstart to stop of the display block 99.

In the first embodiment, a display start instruction to the displayblock 99 is given by the second processor 7 after completion of displaydata processing. According to the third embodiment, the startinstruction is delivered by the second processing block 98 to thedisplay block 99, at Step 115 a shown in FIG. 19. Then, the displayblock 99 is activated at Step 116 and the display change is conducted atStep 117. After the display change is examined at Step 118, the displayblock 99 stops itself at Step 119.

As understood, the third embodiment which is similar in the function tothe first embodiment provides the self-controlled de-energization ofboth the second processing block 98 and the display block 99.

Also, a start instruction to the display block 99 is given by the secondprocessing block 98. Accordingly, the task of the first processing block1 is lessened, whereby the overall processing speed will be increasedand the arrangement itself will be facilitated.

Embodiment 4

FIG. 20 is a block diagram showing a fourth embodiment of the presentinvention, in which an energy saving manner is disclosed with the use ofan input/output port for communications with the outside. A dataprocessing apparatus of the fourth embodiment incorporates aninput/output unit 50 mounted in its data input block 97. Theinput/output unit 50 contains a communications port 51 and an externalinterface 52. In operation, the unit 50 performs actions as shown in atiming chart of FIG. 21 which is similar to the timing chart of key dataentry shown in FIG. 12. When a series of inputs from the communicationsport are introduced at t1 to t74, as shown in FIG. 21-a, theinput/output unit 50 delivers corresponding signals to the firstprocessing block 1. The first processor 4 sends an input data at t1 tothe display circuit 8 which in turn actuates, as shown in FIG. 21-d, fordisplay of a data string as illustrated in FIG. 21 -e. If an input at t7is bulky, the second processor 7 is activated at t71 as shown in FIG.21-c

The second processor 7 delivers a start instruction at t72 to thedisplay circuit 8 which is then actuated for data replacement on thedisplay 2. If the input through the communications port is not bulky, itis processed in the first processor 4 or the input/output unit 50 whilethe second processor 7 remains inactivated. Accordingly, energy savingduring the input and output action will be ensured.

Embodiment 5

FIG. 22 is a block diagram showing a fifth embodiment of the presentinvention, in which a solar battery 60 is added as an extra powersource. The first processor 4 operates at low speeds thus consuming asmall amount of electric energy. Accordingly, the apparatus can bepowered by the solar battery 60. While the action is almost equal tothat of the first embodiment, the solar battery however stops powersupply when the amount of incident light is decreased considerably. Ifthe supply is stopped, it is shifted to from the source 61. When no keyentry is made throughout a length of time and no power supply from thesolar battery 60 is fed, the source stop mode is called for as shown inFIG. 23-b. The first processor 4 saves processing data into the firstmemory 5 and then, stops operation. Thus, the power consumption will bereduced. When a power supply from the solar battery 60 is fed again att71 or another key input data is fed from the data input unit 3, thefirst processor 4 starts actuating for performance of an equal actionfrom t72.

One example of the start procedure of the first processor 4 will now bedescribed. As shown in FIG. 24, a key input device 62 of the data inputunit 3 feeds a voltage from the battery 64 to a hold circuit 63. Thehold circuit 63 upon pressing of a key connects the power source to thefirst processor 4 for energization. Simultaneously, the key input device62 transfers a key input data to the first processor 4 and processingwill start.

Each key of the key input device 62 may have a couple of switches; onefor power supply and the other for data entry.

Accordingly, as the solar battery is equipped, the power consumptionwill be minimized and the operating life of the apparatus will last muchlonger.

The solar battery 60, which becomes inactive when no incoming lightfalls, may be mounted on the same plane as of the display 2 so that nodisplay is made including text and keyboard when the solar battery 60 isinactivated.

Hence, no particular trouble will arise in practice. In case of wordprocessing in the dark e.g. during projection of slide pictures in alecture, a key entry action triggers the hold circuit 3 for actuation ofthe first processor 4.

As the data processing apparatus of the fifth embodiment provides moreenergy saving, it may be realized in the form of a note-sizemicrocomputer featuring no battery replacement for years. Also, thefirst and second processors in any of the first to fifth embodiments maybe integrated to a single unit as shown in FIG. 25.

It was found through experiments of simulative calculation conducted byus that the average power consumption during a word processing programwas reduced from 5 w of a reference value to as small as severalhundredths of a watt when the present invention was associated. Thismeans that a conventional secondary cell lasts hundreds of hours and aprimary cell, e.g. a highly efficient lithium cell, lasts more than 1000hours. In other words, a note-size computer will be available whichlasts, like a pocket calculator, over one year in use of 5-hour a daywithout replacement of batteries. As understood, intensive attempts athigher-speed operation and more-pixel display are concurrently beingprosecuted and also, troublesome recharging of rechargeable batteriesneeds to be avoided. The present invention is intended to free note-sizecomputers from tangling cords and time-consuming rechargers.

The advantages of high speed and high resolution attributed toferroelectric liquid crystal materials have been known.

The present invention in particular focuses more attention on the energysaving effects of the ferroelectric liquid crystal which have been lessregarded.

No such approach has been previously made. The energy saving effectswill surely contribute to low power requirements of portable dataprocessing apparatuses such as note-size computers.

Although the embodiments of the present invention employ a displaydevice of ferroelectric liquid crystal for utilization of memoryeffects, other memory devices of smectic liquid crystal orelectrochromic material will be used with equal success. The liquidcrystal display is not limited to a matrix drive as described and may bedriven by a TFT drive system.

1-18. (canceled)
 19. A computer comprising: an information inputtingsection operable to input information external to the portableinformation processing apparatus; a first processing section; a secondprocessing section operable to perform a predetermined process; and adisplay section operable to display a result of the predeterminedprocess performed by the second processing section, wherein: the firstprocessing section is operable to operate in accordance with a firstclock having a first frequency, the second processing section has anoperation state, a stop state and a power supply stop state, in theoperation state the second processing section operates in accordancewith a second clock having a second frequency, in the stop state thesecond processing section stops operating in accordance with the secondclock while the power supply to the second processing section ismaintained, in the power supply stop state the power supply to thesecond processing section is stopped, the first processing section isoperable, when the second processing section is in the stop state, toprocess the information inputted by the information inputting section,to determine whether it is necessary to initiate the second processingsection and provide to the second processing section, if necessary, anoutput for initiating the second processing section and at least part ofthe information inputted by the information inputting section, thesecond processing section in the stop state is operable to make atransition from the stop state to the operation state based on theoutput for initiating the second processing section output from thefirst processing section, the second processing section in the powersupply stop state is operable to make a transition from the power supplystop state to one of the stop state and the operation state based on anoutput from the first processing section, and the second processingsection in the operation state is operable to perform the predeterminedprocess based on the at least part of the information output from thefirst processing section.
 20. A computer according to claim 19, whereinthe transition from the stop state to the operation state in the secondprocessing section is made by supplying the second clock to the secondprocessing section in the stop state.
 21. A computer according to claim19, wherein the second processing section includes a main processingsection operable to perform the predetermined process based on theinformation output from the first processing section, and the mainprocessing section includes a RAM and a register.
 22. A computeraccording to claim 19, wherein the transition from the power supply stopstate to one of the stop state and the operation state in the secondprocessing section is made by supplying the power to the secondprocessing section in the power supply stop state.
 23. A computeraccording to claim 19, wherein the first processing section is operableto determine whether the information is input into the informationinputting section during a predetermined period, stop the displaysection when the first processing section determines that theinformation is not input into the information inputting section duringthe predetermined period, and initiate the display section when thefirst processing section determines that the information is input intothe information inputting section during the predetermined period.
 24. Acomputer according to claim 23, wherein the information inputtingsection is a keyboard.
 25. A computer according to claim 19, furthercomprising; a back light section operable to provide the display sectionwith light.
 26. A computer according to claim 25, wherein the firstprocessing section is operable to determine whether the information isinput into the information inputting section during a predeterminedperiod, stop the back light section when the first processing sectiondetermines that the information is not input into the informationinputting section during the predetermined period, and initiate the backlight section when the first processing section determines that theinformation is input into the information inputting section during thepredetermined period.
 27. A computer according to claim 26, wherein theinformation inputting section is a keyboard.
 28. A computer comprising:an information inputting section operable to input information externalto the portable information processing apparatus; a first processingsection; a second processing section operable to perform a predeterminedprocess; and a display section operable to display a result of thepredetermined process performed by the second processing section,wherein: the first processing section is operable to operate inaccordance with a first clock having a first frequency, the secondprocessing section has an operation state, a lower-operation state and apower supply stop state, in the operation state the second processingsection operates in accordance with a second clock having a secondfrequency, in the lower-operation state the second processing sectionoperates in accordance with a clock having a frequency which is lowerthan the second frequency while the power supply to the secondprocessing-section is maintained, in the power supply stop state thepower supply to the second processing section is stopped, the firstprocessing section is operable, when the second processing section is inthe lower-operation state, to process the information inputted by theinformation inputting section, to determine whether it is necessary toinitiate the second processing section and provide to the secondprocessing section, if necessary, an output for initiating the secondprocessing section and at least part of the information inputted by theinformation inputting section, the second processing section in thelower-operation state is operable to make a transition from the loweroperation state to the operation state based on the output forinitiating the second processing section output from the firstprocessing section, the second processing section in the power supplystop state is operable to make a transition from the power supply stopstate to one of the lower-operation state and the operation state basedon an output from the first processing section, and the secondprocessing section in the operation state is operable to perform thepredetermined process based on the at least part of the informationoutput from the first processing section.
 29. A computer according toclaim 28, wherein the transition from the lower-operation state to theoperation state in the second processing section is made by supplyingthe second clock to the second processing section in the lower operationstate.
 30. A computer according to claim 28, wherein the secondprocessing section includes a main processing section operable toperform the predetermined process based on the information output fromthe first processing section, and the main processing section includes aRAM and a register.
 31. A computer according to claim 28, wherein thetransition from the power supply stop state to one of lower-operationstate and the operation state in the second processing section is madeby supplying the power to the second processing section in the powersupply stop state.
 32. A computer according to claim 28, wherein thefirst processing section is operable to determine whether theinformation is input into the information inputting section during apredetermined period, stop the display section when the first processingsection determines that the information is not input into theinformation inputting section during the predetermined period, andinitiate the display section when the first processing sectiondetermines that the information is input into the information inputtingsection during the predetermined period.
 33. A computer according toclaim 32, wherein the information inputting section is a keyboard.
 34. Acomputer according to claim 28, further comprising: a back light sectionoperable to provide the display section with light.
 35. A computeraccording to claim 34, wherein the first processing section is operableto determine whether the information is input into the informationinputting section during a predetermined period, stop the back lightsection when the first processing section determines that theinformation is not input into the information inputting section duringthe predetermined period, and initiate the back light section when thefirst processing section determines that the information is input intothe information inputting section during the predetermined period.
 36. Acomputer according to claim 35, wherein the information inputtingsection is a keyboard.